Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components and semiconductor packages. For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, allowing more components to be integrated into a semiconductor chip or package.
One approach for allowing more components to be integrated into a semiconductor structure is the adoption of three dimensional integrated circuit (3D IC) stacking techniques, in which silicon wafers and/or dies are stacked on one another and vertically interconnected using through vias so that they behave as a single device to achieve performance improvements than conventional two dimensional processes. However, conventional techniques for 3D IC stacking merely allow stacking wafers and/or dies on one side of a base substrate/wafer. Accordingly, what is needed are semiconductor structures with wafers and/or dies stacked on both sides of the base substrate/wafer.